Senior FPGA Design Engineer
CV-LibraryCambridge, CambridgeshirepermanentPosted: 24 September 2026
Apply NowSenior FPGA Design Engineer | Hybrid | Cambridge
Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative engineering team, contributing to the core FPGA technology that powers a range of next-generation products.
Responsibilities
*
Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
*
Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
*
Write module specifications, review code and documentation, and maintain high engineering standards.
*
Collaborate with hardware, software, and mechanical engineers to deliver new products to market.
Essential Experience
*
Strong SystemVerilog FPGA design experience.
*
RTL verification skills and familiarity with Python.
*
Experience writing timing constraints and achieving timing closure.
Desirable Experience
*
Experience with cocotb for FPGA verification.
*
Familiarity with Linux command line, Git/SVN, and Markdown.
Do you want to work in a high variety, high complexity environment on highly advanced systems? Apply with your CV & I'll be in touch
Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative engineering team, contributing to the core FPGA technology that powers a range of next-generation products.
Responsibilities
*
Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products.
*
Perform RTL verification and support timing closure through constraints, analysis, and design optimisation.
*
Write module specifications, review code and documentation, and maintain high engineering standards.
*
Collaborate with hardware, software, and mechanical engineers to deliver new products to market.
Essential Experience
*
Strong SystemVerilog FPGA design experience.
*
RTL verification skills and familiarity with Python.
*
Experience writing timing constraints and achieving timing closure.
Desirable Experience
*
Experience with cocotb for FPGA verification.
*
Familiarity with Linux command line, Git/SVN, and Markdown.
Do you want to work in a high variety, high complexity environment on highly advanced systems? Apply with your CV & I'll be in touch